Clock Domain¶
- class torii.hdl.cd.ClockDomain(name: str | None = None, *, clk_edge: Literal['pos', 'neg'] = 'pos', reset_less: bool = False, async_reset: bool = False, local: bool = False) None¶
Synchronous domain.
- Parameters:
name (str | None) – Domain name. If
None(the default) the name is inferred from the variable name thisClockDomainis assigned to (stripping any “cd_” prefix).reset_less (bool) – If
True, the domain does not use a reset signal. Registers within this domain are still all initialized to their reset state once, e.g. through Verilog “initial” statements.clk_edge (str) – The edge of the clock signal on which signals are sampled. Must be one of “pos” or “neg”.
async_reset (bool) – If
True, the domain uses an asynchronous reset, and registers within this domain are initialized to their reset state when reset level changes. Otherwise, registers are initialized to reset state at the next clock cycle when reset is asserted.local (bool) – If
True, the domain will propagate only downwards in the design hierarchy. Otherwise, the domain will propagate everywhere.
- Attributes:
clk (Signal, inout) – The clock for this domain. Can be driven or used to drive other signals (preferably in combinatorial context).
rst (Signal | None, inout) – Reset signal for this domain. Can be driven or used to drive.