Wishbone Bus

class torii.lib.bus.wishbone.Arbiter(*, addr_width: int, data_width: int, granularity: int | None = None, features: Iterable[Literal['rty', 'err', 'stall', 'lock', 'cti', 'bte']] = frozenset({})) → None

Wishbone bus arbiter.

A round-robin arbiter for initiators accessing a shared Wishbone bus.

Parameters:
Attributes:

bus (Interface) – Shared Wishbone bus.

add(intr_bus: Interface) → None

Add an initiator bus to the arbiter.

The initiator bus must have the same address width and data width as the arbiter. The granularity of the initiator bus must be greater than or equal to the granularity of the arbiter.

elaborate(platform) → Module
Return type:

Module

Todo

Document Me

class torii.lib.bus.wishbone.BurstTypeExt(value)

Wishbone Registered Feedback burst type extension.

LINEAR = 0
WRAP_4 = 1
WRAP_8 = 2
WRAP_16 = 3
class torii.lib.bus.wishbone.CycleType(value)

Wishbone Registered Feedback cycle type.

CLASSIC = 0
CONST_BURST = 1
INCR_BURST = 2
END_OF_BURST = 7
class torii.lib.bus.wishbone.Decoder(*, addr_width: int, data_width: int, granularity: int | None = None, features: Iterable[Literal['rty', 'err', 'stall', 'lock', 'cti', 'bte']] = frozenset({}), alignment: int = 0, name: str | None = None) → None

Wishbone bus decoder.

An address decoder for subordinate Wishbone buses.

Parameters:

  • addr_width (int) – Address width. See Interface.

  • data_width (int) – Data width. See Interface.

  • granularity (int) – Granularity. See Interface

  • features (iter(str)) – Optional signal set. See Interface.

  • alignment (log2 of int) – Window alignment. See memory.MemoryMap

  • name (str | None) – Window name.

property bus: Interface

Wishbone bus providing access to subordinate buses.

align_to(alignment: int) → int

Align the implicit address of the next window.

See MemoryMap.align_to() for details.

Return type:

int

add(sub_bus: Interface, *, addr: int | None = None, sparse: bool = False, extend: bool = False) → tuple[int, int, int]

Add a window to a subordinate bus.

The decoder can perform either sparse or dense address translation. If dense address translation is used (the default), the subordinate bus must have the same data width as the decoder; the window will be contiguous. If sparse address translation is used, the subordinate bus may have data width less than the data width of the decoder; the window may be discontiguous. In either case, the granularity of the subordinate bus must be equal to or less than the granularity of the decoder.

See MemoryMap.add_resource() for details.

Return type:

tuple[int, int, int]

elaborate(platform) → Module
Return type:

Module

Todo

Document Me

class torii.lib.bus.wishbone.Interface(*, addr_width: int, data_width: int, granularity: int = None, features: Iterable[Literal['rty', 'err', 'stall', 'lock', 'cti', 'bte']] = frozenset({}), name: str | None = None) → None

Wishbone interface.

See the Wishbone specification for description of the Wishbone signals. The RST_I and CLK_I signals are provided as a part of the clock domain that drives the interface.

Note that the data width of the underlying memory map of the interface is equal to port granularity, not port size. If port granularity is less than port size, then the address width of the underlying memory map is extended to reflect that.

Parameters:

  • addr_width (int) – Width of the address signal.

  • data_width (int) – Width of the data signals (“port size” in Wishbone terminology). One of 8, 16, 32, 64.

  • granularity (int) – Granularity of select signals (“port granularity” in Wishbone terminology). One of 8, 16, 32, 64.

  • features (iter(str)) – Selects the optional signals that will be a part of this interface.

  • name (str) – Name of the underlying record.

Attributes:

  • adr (Signal(addr_width)) – Corresponds to Wishbone signal ADR_O (initiator) or ADR_I (target).

  • dat_w (Signal(data_width)) – Corresponds to Wishbone signal DAT_O (initiator) or DAT_I (target).

  • dat_r (Signal(data_width)) – Corresponds to Wishbone signal DAT_I (initiator) or DAT_O (target).

  • sel (Signal(data_width // granularity)) – Corresponds to Wishbone signal SEL_O (initiator) or SEL_I (target).

  • cyc (Signal()) – Corresponds to Wishbone signal CYC_O (initiator) or CYC_I (target).

  • stb (Signal()) – Corresponds to Wishbone signal STB_O (initiator) or STB_I (target).

  • we (Signal()) – Corresponds to Wishbone signal WE_O (initiator) or WE_I (target).

  • ack (Signal()) – Corresponds to Wishbone signal ACK_I (initiator) or ACK_O (target).

  • err (Signal()) – Optional. Corresponds to Wishbone signal ERR_I (initiator) or ERR_O (target).

  • rty (Signal()) – Optional. Corresponds to Wishbone signal RTY_I (initiator) or RTY_O (target).

  • stall (Signal()) – Optional. Corresponds to Wishbone signal STALL_I (initiator) or STALL_O (target).

  • lock (Signal()) – Optional. Corresponds to Wishbone signal LOCK_O (initiator) or LOCK_I (target). torii-soc Wishbone support assumes that initiators that don’t want bus arbitration to happen in between two transactions need to use lock feature to guarantee this. An initiator without the lock feature may be arbitrated in between two transactions even if cyc is kept high.

  • cti (Signal()) – Optional. Corresponds to Wishbone signal CTI_O (initiator) or CTI_I (target).

  • bte (Signal()) – Optional. Corresponds to Wishbone signal BTE_O (initiator) or BTE_I (target).

Note

The correspondence between the torii.lib.soc signals and the Wishbone signals changes depending on whether the interface acts as an initiator or a target.