Memory

class torii.hdl.mem.DummyPort(*, data_width: int, addr_width: int, domain: str = 'sync', name: str | None = None, granularity: int | None = None) → None

Dummy memory port.

This port can be used in place of either a read or a write port for testing and verification. It does not include any read/write port specific attributes, i.e. none besides 'domain'; any such attributes may be set manually.

Parameters:

  • data_width (int) – The width of the data signal on this port.

  • addr_width (int) – The width of the addr signal on this port.

  • domain (str) – The domain this port is to operate on.

  • name (str | None) – The name of this port.

  • granularity (str | None) – Port granularity if set. If None defaults to data_width.

Attributes:

  • domain (str) – Port domain.

  • addr (Signal(addr_width)) – Port address.

  • data (Signal(data_width)) – Port data.

  • en (Signal(data_width // granularity)) – Port enable bitmask.

class torii.hdl.mem.Memory(*, width: int, depth: int, init: Sequence[int] | None = None, name: str | None = None, attrs: OrderedDict | None = None, simulate: bool = True) → None

A word addressable storage.

Parameters:

  • width (int) – Access granularity. Each storage element of this memory is width bits in size.

  • depth (int) – Word count. This memory contains depth storage elements.

  • init (collections.abc.Sequence[int]) – Initial values. At power on, each storage element in this memory is initialized to the corresponding element of init, if any, or to zero otherwise. Uninitialized memories are not currently supported.

  • name (str | None) – Name hint for this memory. If None the name is inferred from the variable name this Memory is assigned to.

  • attrs (dict | None) – Dictionary of synthesis attributes.

Attributes:

  • width (int) – Width of each element in this memory.

  • depth (int) – Number of elements in this memory.

  • init (list[int]) – Initial values for this memory.

  • attrs (dict) – Synthesis attributes.

property init

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read_port(*, domain: str = 'sync', transparent: bool = True, src_loc_at: int = 0) → ReadPort

Get an instance of ReadPort that is associated with this memory.

See ReadPort for details.

Parameters:

  • domain (str) – The domain this ReadPort operates on.

  • transparent (bool) – Port transparency.

Return type:

ReadPort

Returns:

ReadPort – A read-port for this memory.

write_port(*, domain: str = 'sync', granularity: int | None = None, src_loc_at: int = 0) → WritePort

Get an instance of WritePort that is associated with this memory.

See WritePort for details.

Parameters:

  • domain (str) – The domain this WritePort operates on.

  • granularity (int | None) – Port granularity

Return type:

WritePort

Returns:

WritePort – A write-port instance for this memory.

elaborate(platform)

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class torii.hdl.mem.ReadPort(memory: Memory, *, domain: str = 'sync', transparent: bool = True, src_loc_at: int = 0) → None

A memory read port.

Parameters:

  • memory (Memory) – Memory associated with the port.

  • domain (str) – The clock domain this port operates on. If set to the 'comb' domain, the port is asynchronous, otherwise reads have a latency of 1 clock cycle.

  • transparent (bool) – Port transparency. If set a read at an address that is also being written to in the same clock cycle will output the new value. Otherwise, the old value will be output first. This behavior only applies to ports in the same domain.

Attributes:

  • memory (Memory) – The memory associated to this port.

  • domain (str) – The clock domain this port operates on.

  • transparent (bool) – If port transparency is enabled.

  • addr (Signal(range(memory.depth)), in) – Read address.

  • data (Signal(memory.width), out) – Read data.

  • en (Signal | Const) – Read enable. If asserted, data is updated with the word stored at addr.

Raises:

ValueError – If the read port is simultaneously asynchronous and non-transparent.

elaborate(platform)

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class torii.hdl.mem.WritePort(memory: Memory, *, domain: str = 'sync', granularity: int | None = None, src_loc_at: int = 0) → None

A memory write port.

Parameters:

  • memory (Memory) – Memory associated with the port.

  • domain (str) – The clock domain this port operates on. Writes have a latency of 1 clock cycle.

  • granularity (int | None) – Port granularity. Write data is split evenly in memory.width // granularity chunks, which can be updated independently. If None defaults to memory.width.

Attributes:

  • memory (Memory) – The memory associated to this port.

  • domain (str) – The clock domain this port operates on.

  • granularity (int) – The port granularity.

  • addr (Signal(range(memory.depth)), in) – Write address.

  • data (Signal(memory.width), in) – Write data.

  • en (Signal(memory.width // granularity), in) – Write enable. Each bit selects a non-overlapping chunk of granularity bits on the data signal, which is written to memory at addr. Unselected chunks are ignored.

Raises:

ValueError – If the write port granularity is greater than memory width, or does not divide memory width evenly.

elaborate(platform)

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