Memory
Warning
The Torii API reference is a work in progress and we are actively working on improving it, however it may be deficient or missing in places.
- class torii.hdl.mem.DummyPort(*, data_width, addr_width, domain='sync', name=None, granularity=None)
Dummy memory port.
This port can be used in place of either a read or a write port for testing and verification. It does not include any read/write port specific attributes, i.e. none besides
'domain'
; any such attributes may be set manually.
- class torii.hdl.mem.Memory(*args, src_loc_at: int = 0, **kwargs)
A word addressable storage.
- Parameters:
width (int) – Access granularity. Each storage element of this memory is
width
bits in size.depth (int) – Word count. This memory contains
depth
storage elements.init (list of int) – Initial values. At power on, each storage element in this memory is initialized to the corresponding element of
init
, if any, or to zero otherwise. Uninitialized memories are not currently supported.name (str) – Name hint for this memory. If
None
(default) the name is inferred from the variable name thisSignal
is assigned to.attrs (dict) – Dictionary of synthesis attributes.
- Variables:
- class torii.hdl.mem.ReadPort(*args, src_loc_at: int = 0, **kwargs)
A memory read port.
- Parameters:
memory (
Memory
) – Memory associated with the port.domain (str) – Clock domain. Defaults to
'sync'
. If set to'comb'
, the port is asynchronous. Otherwise, the read data becomes available on the next clock cycle.transparent (bool) – Port transparency. If set (default), a read at an address that is also being written to in the same clock cycle will output the new value. Otherwise, the old value will be output first. This behavior only applies to ports in the same domain.
- Variables:
- Raises:
- class torii.hdl.mem.WritePort(*args, src_loc_at: int = 0, **kwargs)
A memory write port.
- Parameters:
memory (
Memory
) – Memory associated with the port.domain (str) – Clock domain. Defaults to
"sync"
. Writes have a latency of 1 clock cycle.granularity (int) – Port granularity. Defaults to
memory.width
. Write data is split evenly inmemory.width // granularity
chunks, which can be updated independently.
- Variables:
memory (
Memory
)domain (str)
granularity (int)
data (Signal(memory.width), in) – Write data.
en (Signal(memory.width // granularity), in) – Write enable. Each bit selects a non-overlapping chunk of
granularity
bits on thedata
signal, which is written to memory ataddr
. Unselected chunks are ignored.
- Raises:
divide memory width evenly. –