Memory¶
Warning
The Torii API reference is a work in progress and we are actively working on improving it, however it may be deficient or missing in places.
- class torii.hdl.mem.DummyPort(*, data_width: int, addr_width: int, domain: str = 'sync', name: str | None = None, granularity: int | None = None)¶
Dummy memory port.
This port can be used in place of either a read or a write port for testing and verification. It does not include any read/write port specific attributes, i.e. none besides
'domain'
; any such attributes may be set manually.- Parameters:
data_width (int) – The width of the
data
signal on this port.addr_width (int) – The width of the
addr
signal on this port.domain (str) – The domain this port is to operate on. (default: ‘sync’)
name (str | None) – The name of this port. (default: None)
granularity (str | None) – Port granularity if set. If
None
defaults todata_width
. (default: None)
- Attributes:
domain (str) – Port domain.
addr (Signal(addr_width)) – Port address.
data (Signal(data_width)) – Port data.
en (Signal(data_width // granularity)) – Port enable bitmask.
- class torii.hdl.mem.Memory(*args: Any, src_loc_at: int = 0, **kwargs: Any)¶
A word addressable storage.
- Parameters:
width (int) – Access granularity. Each storage element of this memory is
width
bits in size.depth (int) – Word count. This memory contains
depth
storage elements.init (Sequence[int]) – Initial values. At power on, each storage element in this memory is initialized to the corresponding element of
init
, if any, or to zero otherwise. Uninitialized memories are not currently supported.name (str | None) – Name hint for this memory. If
None
the name is inferred from the variable name thisMemory
is assigned to. (default: None)attrs (dict | None) – Dictionary of synthesis attributes. (default: None)
- Attributes:
width (int) – Width of each element in this memory.
depth (int) – Number of elements in this memory.
init (list of int) – Initial values for this memory.
attrs (dict) – Synthesis attributes.
- read_port(*, domain: str = 'sync', transparent: bool = True, src_loc_at: int = 0) ReadPort ¶
Get an instance of
ReadPort
that is associated with this memory.See
ReadPort
for details.
- class torii.hdl.mem.ReadPort(*args: Any, src_loc_at: int = 0, **kwargs: Any)¶
A memory read port.
- Parameters:
memory (Memory) – Memory associated with the port.
domain (str) – The clock domain this port operates on. If set to the
'comb'
domain, the port is asynchronous, otherwise reads have a latency of 1 clock cycle. (default:'sync'
)transparent (bool) – Port transparency. If set a read at an address that is also being written to in the same clock cycle will output the new value. Otherwise, the old value will be output first. This behavior only applies to ports in the same domain. (default: True)
- Attributes:
memory (Memory) – The memory associated to this port.
domain (str) – The clock domain this port operates on.
transparent (bool) – If port transparency is enabled.
addr (Signal(range(memory.depth)), in) – Read address.
data (Signal(memory.width), out) – Read data.
en (Signal or Const, in) – Read enable. If asserted,
data
is updated with the word stored ataddr
.
- Raises:
- class torii.hdl.mem.WritePort(*args: Any, src_loc_at: int = 0, **kwargs: Any)¶
A memory write port.
- Parameters:
memory (Memory) – Memory associated with the port.
domain (str) – The clock domain this port operates on. Writes have a latency of 1 clock cycle. (default:
'sync'
)granularity (int | None) – Port granularity. Write data is split evenly in
memory.width // granularity
chunks, which can be updated independently. IfNone
defaults tomemory.width
. (default: None)
- Attributes:
memory (Memory) – The memory associated to this port.
domain (str) – The clock domain this port operates on.
granularity (int) – The port granularity.
addr (Signal(range(memory.depth)), in) – Write address.
data (Signal(memory.width), in) – Write data.
en (Signal(memory.width // granularity), in) – Write enable. Each bit selects a non-overlapping chunk of
granularity
bits on thedata
signal, which is written to memory ataddr
. Unselected chunks are ignored.
- Raises:
divide memory width evenly. –