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Torii-HDL 0.7.8.dev60 documentation
Torii-HDL 0.7.8.dev60 documentation
  • Introduction
  • Installation
  • Getting Started
  • Tutorials
    • Including External non-Torii Modules
  • Language Guide
  • API Reference
    • Torii Backends
    • Torii HDL Reference
      • Abstract Syntax Tree
      • Clock Domain
      • DSL
      • IR
      • Memory
      • Records
      • XFRM
    • Torii Utility Library
      • String Helpers
      • Tracer
      • Unit Helpers
  • Standard Library
    • Busses
      • Wishbone Bus
    • Encoding and Decoding
    • Memory
      • Memory Map
    • Clock Domain Crossing
    • First-in First-out Queues
    • System on Chip
      • Events
      • Peripherals
      • CSRs
    • Industry Standard I/O
    • Stream Library
      • Simple Streams
    • FPGA Vendor Modules
      • Lattice FPGA Modules
      • Xilinx FPGA Modules
  • Platform Integration
    • Torii FPGA Platforms
      • Gowin
      • Altera
      • Lattice ECP5
      • Lattice iCE40
      • Lattice MachXO2 and MachXO3L
      • Quicklogic
      • Xilinx
  • Testing and Verification
    • Simulation
    • Formal Verification
  • External Libraries
  • Torii v0.X to v1.0 Migration Guide
  • Projects Using Torii
  • Torii Boards

Development

  • Source Code
  • Contributing
  • Changelog
  • License
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BussesΒΆ

The torii.lib.bus module provides industry standard bus interfaces, crossbars, and other utilities for busses such as Wishbone.

  • Wishbone Bus
    • CycleType
    • BurstTypeExt
    • Interface
    • Decoder
    • Arbiter
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Wishbone Bus
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Standard Library
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