Torii-HDL
  • Introduction
    • The Torii language
    • The Torii standard library
    • The Torii simulator
    • The Torii build system
    • FPGA toolchain integration
    • Development board definitions
  • Installation
    • System requirements
    • Installing Prerequisites
      • Installing Python
      • Installing Yosys and GTKWave
    • Installing Torii
      • Latest release
      • Development snapshot
      • Editable development snapshot
    • Installing board definitions
      • Latest release
      • Development snapshot
      • Editable development snapshot
  • Getting Started
    • A counter
      • Implementing a counter
      • Testing a counter
      • Converting a counter
    • A blinking LED
  • Tutorials
    • Including External non-Torii Modules
      • Torii Instance
      • Including External Sources
  • Language Guide
    • The prelude
    • Shapes
    • Shapes of values
    • Values
    • Constants
    • Shape casting
      • Shapes from integers
      • Shapes from ranges
      • Shapes from enumerations
    • Value casting
      • Values from integers
      • Values from enumeration members
  • Constant casting
    • Signals
      • Signal shapes
      • Signal names
      • Initial signal values
      • Reset-less signals
    • Operators
      • Performing or describing computations?
      • Width extension
      • Arithmetic operators
      • Comparison operators
      • Bitwise, shift, and rotate operators
      • Reduction operators
      • Logical operators
      • Bit sequence operators
      • Conversion operators
      • Choice operator
    • Modules
      • Control domains
      • Assigning to signals
      • Assignment targets
      • Assignment domains
      • Assignment order
      • Control structures
      • Active and inactive assignments
      • Combinatorial evaluation
      • Synchronous evaluation
  • API Reference
    • Torii Backends
      • CXXRTL Backend
        • YosysError
      • RTLIL Backend
      • Verilog Backend
        • YosysError
    • Torii HDL Reference
      • Abstract Syntax Tree
        • Array
        • Cat
        • ClockSignal
        • Const
        • Initial
        • Mux()
        • ResetSignal
        • Sample
        • Shape
        • ShapeCastable
        • ShapeLike
        • Signal
        • SignalDict
        • SignalKey
        • SignalSet
        • signed()
        • unsigned()
        • ValueCastable
        • ValueDict
        • ValueSet
      • Clock Domain
        • ClockDomain
        • DomainError
      • DSL
        • SyntaxError
        • SyntaxWarning
      • IR
        • DriverConflict
        • Instance
        • UnusedElaboratable
      • Memory
        • DummyPort
        • Memory
        • ReadPort
        • WritePort
      • Records
        • DIR_FANIN
        • DIR_FANOUT
        • DIR_NONE
        • Direction
        • Record
      • XFRM
  • Standard Library
    • Code Conversion
      • One-hot coding
        • Encoder
        • Decoder
      • Priority coding
        • PriorityEncoder
        • PriorityDecoder
      • Gray coding
        • GrayEncoder
        • GrayDecoder
    • Clock Domain Crossing
      • FFSynchronizer
      • AsyncFFSynchronizer
      • ResetSynchronizer
      • PulseSynchronizer
    • First-in First-out Queues
      • FIFOInterface
      • SyncFIFO
      • SyncFIFOBuffered
      • AsyncFIFO
      • AsyncFIFOBuffered
    • System on Chip
      • Events
        • Source
        • EventMap
        • Monitor
      • Memory Map
        • ResourceInfo
        • MemoryMap
      • Peripherals
        • ConstantValue
        • ConstantBool
        • ConstantInt
        • ConstantMap
        • PeripheralInfo
      • CSRs
        • Bus
        • Events
        • Wishbone
      • Wishbone Bus
        • CycleType
        • BurstTypeExt
        • Interface
        • Decoder
        • Arbiter
    • Industry Standard I/O
      • Serial I/O
        • AsyncSerialRX
        • AsyncSerialTX
        • AsyncSerial
    • FPGA Vendor Modules
      • Lattice FPGA Modules
        • iCE40 Blocks
      • Xilinx FPGA Modules
  • Platform Integration
    • Torii FPGA Platforms
      • Intel
        • GowinPlatform
      • Intel
        • AlteraPlatform
      • Lattice ECP5
        • ECP5Platform
      • Lattice iCE40
        • ICE40Platform
      • Lattice MachXO2 and MachXO3L
        • MachXO2Platform
        • MachXO3LPlatform
        • MachXO2Or3LPlatform
      • Quicklogic
        • QuicklogicPlatform
      • Xilinx
        • XilinxPlatform
  • Simulation Framework
  • Changelog
    • Unreleased
      • Added
      • Changed
      • Deprecated
      • Removed
      • Fixed
    • 0.7.1
      • Fixed
    • 0.7.0
      • Added
      • Changed
      • Deprecated
      • Removed
      • Fixed
    • 0.6.2
      • Fixed
    • 0.6.1
      • Fixed
    • 0.6.0
      • Added
      • Changed
      • Deprecated
      • Removed
      • Fixed
    • 0.5.0
      • Added
      • Changed
      • Deprecated
      • Removed
      • Fixed
    • 0.4.5
      • Added
      • Changed
      • Deprecated
      • Removed
      • Fixed
    • 0.4.4
      • Added
      • Changed
      • Deprecated
      • Removed
      • Fixed
    • 0.4.3
      • Fixed
    • 0.4.2
      • Fixed
    • 0.4.1
      • Fixed
    • 0.4.0
      • Added
      • Changed
      • Removed
      • Fixed
    • 0.1.0 - 0.3.0
  • Projects Using Torii
  • Torii Boards
  • Source Code
Torii-HDL
  • Search

© Copyright 2022, Shrine Maiden Heavy Industries.

Built with Sphinx using a theme provided by Read the Docs.